W971GG8JB-25【PDF 47/87 页】IC DDR2 SDRAM 1GBIT 60WBGA

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录369

43页 44页 45页 46页 [47页]48页 49页 50页 51页

W971GG8JB

Notes:

1. All voltages are referenced to V SS .

2. Tests for AC timing, I DD , and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is

disabled for all measurements that are not ODT-specific.

3. AC timing reference load:

VDDQ

DUT

DQS, DQS

RDQS, RDQS

Output

Timing

reference

25 Ω

VTT = VDDQ/2

point

Figure 16

– AC timing reference load

4. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min)

have been satisfied.

5. If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ

can be executed.

6. This is an optional feature. For detailed information, please refer to “ Operating Temperature Condition ” section 10.2 in

this data sheet.

7. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the

valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not

transition from its valid level during the time period of tIS + 2 x tCK + tIH.

8. A minimum of two clocks (2 * nCK) is required irrespective of operating frequency.

9. tWTR is at least two clocks (2 * nCK) independent of operation frequency.

10. There are two sets of values listed for Command/Address input setup time: tIS(base) and tIS(ref). The tIS(ref) value (for

reference only) is equivalent to the baseline value of tIS(base) at VREF when the slew rate is 1.0 V/nS. The baseline value

tIS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level for a rising signal and

VIL(ac) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to

1.0 V/nS, then the baseline values must be derated by adding the values from table of tIS/tIH derating values for DDR2-667,

DDR2-800 and DDR2-1066 (page 55).

CLK

t IS(base) t IH(base)

Logic levels

V DDQ

V IH(ac) min

V IH(dc) min

V REF(dc)

V IL(dc) max

V IL(ac) max

V SS

V REF levels

t IS(ref)

t IH(ref)

t IS(ref)

t IH(ref)

Figure 17

– Differential input waveform timing – tIS and tIH

Publication Release Date: Jun. 15, 2012

- 47 -

Revision A02

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

我的联系方式

相关代理商/技术参数

W9725G6IB-25 功能描述:IC DDR2-800 SDRAM 256MB 84-WBGA RoHS:是类别:集成电路 (IC) >> 存储器系列:- 标准包装:1,000 系列:- 格式 - 存储器:EEPROMs - 串行存储器类型:EEPROM 存储容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 线串口电源电压:2.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.173"，4.40mm 宽）供应商设备封装:8-MFP 包装:带卷 (TR)

W9725G6JB 制造商:WINBOND 制造商全称:Winbond 功能描述:4M ? 4 BANKS ? 16 BIT DDR2 SDRAM

W9725G6JB-25 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:512MB DDRII

W9725G6JB25I 功能描述:IC DDR2 SDRAM 256MBIT 84WBGA RoHS:是类别:集成电路 (IC) >> 存储器系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘供应商设备封装:8-DFN（2x3）包装:管件产品目录页面:1445 (CN2011-ZH PDF)

W9725G6KB-18 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY

W9725G6KB-25 功能描述:IC DDR2 SDRAM 256MBIT 84WBGA RoHS:是类别:集成电路 (IC) >> 存储器系列:- 标准包装:1 系列:- 格式 - 存储器:闪存存储器类型:闪存 - NAND 存储容量:4G（256M x 16）速度:- 接口:并联电源电压:2.7 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽）供应商设备封装:48-TSOP I 包装:Digi-Reel® 其它名称:557-1461-6

W9725G6KB-25 TR 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X16

W9725G6KB25A 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask

我
采购
搜索
会员

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式